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introduction the l6234 is a dmoss triple half-bridge driver with input supply voltage up 52v and output current of 5a. it can be used in a very wide range of applications. it has been realized in multipower bcd60ii technology which allows the combination of isolated dmos transistors with cmos and bipolar circuits on the same chip. it is available in power dip 20 (16+2+2) and in power so 20 packages. all the inputs are ttl/cmos compatible and each half bridge can be driven by its own dedicated input and enable. the dmos structure has an intrinsic free wheeling body diode so the use of external diodes, which are necessary in the bipolar configuration, can be avoided. the dmos structure allows a very low quiescent current of 6.5 ma typ. at vs=42v , irrespective of the load. device description the device is composed of three channels. each channel is composed of a half bridge with two power dmos switches ( typ. rdson of 300mw @ 25 c) and intrinsic free wheeling diodes. each channel in- cludes two ttl/cmos and up compatible comparators, and a logic block to interface the inputs with the drivers. the device includes an internal bandgap reference of 1.22v, a 10v voltage reference to supply the internal circuitry of the device, a central charge pump to drive the upper dmos switch, thermal shut- down protection and an internal hysteretic function which turns off the device when the junction tempera- ture exceeds approximately 160 c. hysteresys is about 20 c. april 2001 ? AN1088 application note l6234 three phase motor driver by domenico arrigo charge pump v ref 10v c3 10nf c5 1 m f vref vcp c4 220nf vs c2 100nf c1 100 m f thermal protection t1 t2 t3 t4 t5 t6 vboot d2 1n4148 out1 out2 sense1 out3 sense2 in1 en1 in2 en2 in3 en3 d98in940a r sense gnd d1 1n4148 vs brushless motor windings vs figure 1. l6234 block diagram 1/14
pin description. vs ( input supply voltage pins). these are the two input supply voltage pins. the unregulated input dc voltage can range from 7v to 52v. with inductive loads the recommended operating maximum supply voltage is 42v to prevent overvoltage applied to the dmosfets. in fact considering a full bridge configuration (see fig. 2), when the bridge is switched off (enable chopping) the current recirculation produces a negative voltage to the source of the lower dmos switches (point a). in this condi- tion the drain-source voltage of t 1 and t 4 is v s +v f +v sense . dinamically v f can be same volts depending on the current slope, di/dt, and also v sense , depending on the parasitic in- ductance and current slope can be some volts. so the drain- source voltage of t1 and t4 dmos switches can reach more than 10v over the v s voltage. the input capacitors c1 and c2 are chosen in order to reduce overvoltage due to current decay and to parasitic inductance. for this reason c2 has to be placed as closed as pos- sible to v s and gnd pins. the device can sustain a 4a dc input current for each of the two vs pins, in accordance with the power dissipation. out1, out2, out3 (outputs). these are the output pins that correspond to the mid point of each half bridge. they are designed to sustain a dc current of 4a. sense1, sense2. sense1 is the common source of the lower dmos of the half bridge 1 and 2. sense2 is the source of the lower dmos of the half bridge 3. each of these pins can handle a current of 5a. a resistance, rsense, connected to these pins provides feed- back for motor current control. care must be taken with the negative voltage applied to these pins : negative dc voltage lower than -1v could damage the device. for duration lower than 300ns the device can sustain pulsed negative voltage up to -4v. for example, if enable chopping current control method is used, negative voltage pulses appear to these pins, due to the current recirculation through the sensing resistor. vref ( voltage reference). this is the internal 10v voltage reference pin to bias the logic and the low voltage circuitry of the device. a 1 m f electrolytic ca- pacitor connected from this pin to gnd ensures the stability of the dmos drive circuit. this pin can be externally loaded up to 5ma . figure 3 and 4 show the typical behaviorof the vref pin. vcp ( charge pump ). this is the internal oscillator output pin for the charge pump. the oscillator supplied by the 10v voltage reference switches from gnd to 10v with a typical frequency of -50 -25 0 25 50 75 100 125 150 0 1 2 3 4 5 6 7 8 9 10 11 tj [ c] vref [v] vs = 52v vs = 24v vs = 7v vs = 10v figure 3. reference voltage vs. junction temperature. 0 1020304050 0 2 4 6 8 10 12 vs [v] vref [v] tj = 25 c figure 4. reference voltage vs. supply voltage. l on/off on/off t1 c t3 t2 t4 b a (v s +v f ) -v sense -v f v s v f on off rsense d98in938a s figure 2. AN1088 application note 2/14
1.2mhz (see fig 4). when the oscillator output is at ground , c3 is charged by vs through d1. when it rises to 10v, d1 is reverse biased and the charge flows from c3 to c4 through d2, so the vboot pin af- ter a few cycles reaches the maximum voltage of vs + 10v - vd1- vd2. vboot ( bootstrap). this is the input bootstrap pin which gives the overvoltage necessary to drive all the upper dmos of the three half bridges (see fig 5). logic inputs pins. en1, en2, en3 (enables). these pins are ttl/cmos and m p compatible. each half bridge can be enabled by its own dedicated pin with a logic high. the logic low on these pins switches off the related half bridge (see fig. 6). the maximum switching frequency is 50khz. in1, in2, in3 (inputs). these pins are ttl/cmos and m p compatible. they allow switching on the upper dmos ( input at high logic level) or the lower dmos (input at low logic level) in each half bridge (see fig. 6). 10nf vcp 1n4148 0.22 m f vboot 1n4148 charge pump vref 10v 0.1 m f vs 100 m f high side driver vs+vref-vd1-vd2 vref f=1.2 mhz vs+vref-vd1 vs-vd1 f=1.2 mhz d1 d2 c3 c4 c2 c1 out vs sense figure 5. charge pump circuit. upper dmos lower dmos dmos on dmos off dmos on time time dmos off enable high level low level time dmos off input time high level low level low level high level high level dmos off low level dmos off dmos off figure 6. control logic for each half bridge. tdelay 300ns tdelay 300ns input pin upper dmos lower dmos high level low level dmos on dmos off dmos on dmos off time time time dmos off dmos on low level figure 7. cross conduction protection. AN1088 application note 3/14
cross conduction protection (see fig. 7) avoids simultaneously turning on both the upper and lower dmos of each half bridge. there is a fixed delay time of 300ns between the turn on and the turn off of the two dmos switches in each half bridge. the switching operating frequency is up 50khz. high com- mutation frequency permits the reduction of ripple of the output current but increases the device's power dissipation, however low commutation frequency causes high ripple of the output current. the switching frequency should be higher than 16khz to avoid acoustic noises. the sink current at the inputs and enables pins is approximately 30 m a if the voltage to these pins is at least 1v less than the vref voltage (see fig. 3 and fig. 4). to avoid overload of the logic inputs and enables , voltage should be applied to vs prior to the logic signal inputs. power dissipation an evaluation of the power dissipation of the ic driving a three phase motor in a chopping current con- trol application follows. with a simplified approach it can be distinguished three periods (see fig. 8) : rise time, tr, period. this is the rise time period, tr, in which the cur- rent switches from one winding to another. in this time a dmos is switched on and the current in- creases up to the peak value ipk with the law i(t) = (ipk/tr) t. the energy lost for the rise time in the period t is : erise = 0 tr rdson ? i 2 ( t ) dt = rdson ? i 2 pk ? tr 3 fall time,tf, period. when the current switches from one winding to another, there is a fall time in which the current that flows in the intrisic diode of the dmos de- creases from ipk to zero. if vd is the voltage fall of the diode, the energy lost is : efall = 0 tf vd ( t ) ? i ( t ) dt tload during this time the current that flows in the winding is limited by the chopping current control. the en- ergy dissipated due to the on resistance of the dmos is : eload = rdson ? ( i rms ) 2 ? tload in the formula, irms is the rms load current, given by : irms = ``````````` ( iload ) 2 + ? ? ? i pk - ival ` ` 3 ? ? ? 2 and iload is the average load current. when the switch is on, the energy dissipated due to the commutation of the chopping current control in the dmos can be assumed to be: eon = vs ? ival ? tcom 2 where tcom is the commutation time of the dmos switch. trise tfall tload tchop ipk ival iload figure 8. AN1088 application note 4/14
when the switch is off : eoff = vs ? ipk ? tcom 2 the energy lost by commutation in a chopping period, given by eon + eoff, is : ecom = vs ? iload ? tcom the energy lost by commutation during the tload time is given by : ecom = vs ? iload ? tcom ? tload ? fchop quiescent power dissipation, pq. the power dissipation due to the quiescent current is pq = vs ? iq , in which iq is the quiescent current at the chopping frequency, fchop = 1/tchop. total power dissipation . let's evaluate the power dissipation of the device driving a three phase brushless motor in chopping cur- rent control. in the driving sequence only one upper dmos and a lower one are on at the same time (see fig. 9 and 10). the total power dissipation is given by : ptot = 2 ? ( erise + efall + eload + ecom ) t + pq figure 11 shows the total power dissipation, pd, of the l6234 driving a three phase brushless motor in input chopping current control at different chopping frequency. evaluation board. the l6234 power so20 board has been realized to evaluate the device driving, in closed loop control, a three phase brushless motor with open collector hall effect sensors. iload i1b i1a i2b half bridge 1 half bridge 2 out1 out2 i1b i2b i1a iload vs on/off off/on on off _ phase 12 chopping input ioff figure 9. input chopping current circulation. AN1088 application note 5/14
the device soldered on the copper heat dissipating area on the board ,without any additional heat sink, can sustain a dc load current of 2.3 a at t amb of approximately 40 c. the board provides a closed loop speed and torque control, with a constant toff chopping current con- trol method. it allows the user to change the direc- tion and brake the motor. constant t off chopping current control. when the current through the motor exceeds the threshold, fixed by the ratio between the control voltage vcontrol and the sensing resistor, rsense, an error signal is generated, the output of the lm393 comparator switches to ground. this state is maintained by the monostable (m74hc123) for a constant delay time ( t off ) generating a pwm sig- nal that achieves the chopping current control. the pwm signal is used for chopping the input pat- tern. during the toff in chopping current control, the current flows in the low side loop ( see fig. 9 ) and does not flow through the sensing resistor. the t off value can be set by the r9 and c11 to values shown in the table 1. a suitable value of toff for the majority of applications is 30 m s. the larger the t off , the higher is the cur- rent ripple. if the t off is too large the ripple current becomes excessive . on the other hand if the t off is too small the winding current cannot decrease under the threshold and current regulation is not guaran- teed. iout1 iout2 iout3 t out3 l6234 out2 out1 brushless motor figure 10. three phase brushless motor control sequence. 01 2 3 45 0 iload [a] pd [w] dc fchop=30khz fchop=50khz 15 10 5 input chopping vs=36v l=2mh t=2ms tj=100c figure 11. l6234 power dissipation in three phase brushless motor control. AN1088 application note 6/14
torque & speed closed loop control. the motor's rotational speed is determined by the frequency of the hall effect signals. the speed control loop has been achieved by comparing this frequency with a frequency of a reference oscillator (see fig. 14) that corresponds to a desired speed limit. 3 out3 l6234 c1 100uf 60v en3 in3 in2 in1 en1 en2 out2 out1 vboot vcp vs 7 912 17 18 6 5 15 4 14 8 13 d1 d2 c4 c3 10nf c2 220nf 100nf 1n4148 1n4148 power so20 1 2 gnd +5v vref 10 11 20 16 19 c5 1uf r10 10k each in2 in1 in3 en3 en2 en1 sense r1 r2 r3 r4 reference speed constant toff chopping current control vsense vcontrol torque & speed control pwm brushless motor hall effect sensors control logic hall effect signals brake dir pwm hall effect signal c6 220nf 1 2 in 3 out l7805 gnd 10uf c7 z1 18v r5 10k t1 +5v j7 reference speed vs=8v to 42 1 w 1 w 1 w 1 w figure 12. application board schematic circuit. m74hc123 monostable +5v +5v c11 330pf r9 100nf c10 23 16 4 15 14 8 1 10 0k r11 10k vcon trol pwm +5v 100nf lm393 r7 11 k r8 1k c8 47 0pf r6 1k 2 vsense 1 +5v 8 3 4 + - c9 _ q a b +5v j1 figure 13. constant toff current control. toff r9 c11 20 m s 100k 270pf 30 m s 100k 330pf 45 m s 100k 560pf 70 m s 100k 1nf table 1. toff selection phase/ frequency detector hall sensors compensation network pwm vcontrol amp. motor reference feedback d01in1209 figure 14. pll motor control. AN1088 application note 7/14
when the hall effect signal fre- quency is lower than the reference frequency, the control voltage is maintained to a value that sets the motor current limit and therefore the torque control limit. the peak cur- rent limit is given by ipeak = vcon- trol/rsense. when the frequency from the hall effect sensors exceeds the refer- ence frequency and an error signal is generated by the pll (see fig. 14). an lm358 comparator, a loop amplifier and an auxiliary op-amp ensure the right gain and filtering to guarantee the stability (see fig.16). the error signal causes vcontrol decrease to a value that sets the pwm chopping current control in or- der to reduce the torque and set the desired speed. the motor speed is regulated to within 0.02 % of the desired speed. control logic circuit. the logic sequence to the motor is generated by a gal16v8, which decodes the hall effect signals and generates the input and enable pattern shown in fig. 18. the brake function is obtained by setting the input pattern to logic low and thus turning on the lower dmos switches of the enabled half- bridges. the pwm signal is used for chop- ping the input pattern. the control logic circuit decodes hall effect sensors having different phasing. with the dir jumper opened the application achieves forward rota- tion for motors having 60 and 120 hall effect sensor electrical phasing and the reverse rotation for motors having 300 and 240 hall effect sensor phasing. connecting the dir jumper to ground sets the reverse rotation for motors having 60 and 120 hall sensors phasing and the forward rotation for motors having 300 and 240 hall sensor phasing. the sw2 switch performs the start- stop function. referencespeed ne555 100nf c21 4 7 1 +5v 100nf 2 r27 16k c20 r26 36k 5 3 8 6 100nf c19 figure 15. oscillator for reference speed. r16 270k 3 1 gnd +5v 7 9 12 6 5 15 13 14 810 11 2 4 16 c15 100nf bat47 hall1 (speed feedback) +5v +vin 100nf c14 c13 1uf 3635 +5v vcontrol +5v 5k r14 47k r13 47k r20 r15 47k r18 33k c16 220nf c17 47nf r19 91k r21 91k r17 10m lm358 +5v r12 47k 2 1 c12 100nf 8 3 4 + - p2 1k p1 gnd reference speed tp8 phase/ frequency detector 2.5v loop amplifier aux. op-amp out put figure 16. phase locked loop and filtering. 100nf c18 2 3 gal 16v8 4 19 1 6 10 5 20 pwm +5v pwm brake dir hall1 hall2 hall3 en1 en2 en3 in1 in2 in3 16 15 14 18 17 brake dir gnd +5v motor hall effect signals direction change dir =0 gnd : back rotation dir = 5v : forward rotation brake function brake = gnd : brake brake = 5v : go in2 in1 in3 en3 en2 en1 7 +5v r25 10k r26 10k r22 10k r23 10k r24 10k r29 10k sw1 j1 sw2 figure 17. control logic circuit. AN1088 application note 8/14
0 hall1 d98in912 hall2 hall3 sensor signals en1 en2 en3 enable in1 in2 in3 forward rotation in1 in2 in3 reverse rotation iout1 iout2 iout3 motor drive current in forward rotation no pwm pwm constant t off electrical degrees 0 0 0 360 figure 17. AN1088 application note 9/14
layout considerations. special attention must be taken to avoid overvoltages at vs and additional negative voltages to the sense pins and noise due to distributed inductance. thus the input capacitor must be connected close to the vs pins with symmetrical paths. the paths between the sense pins and the input capacitor ground have to be minimized and symmetrical . the sensing resistors must be non-inductive. the de- vice gnd has to be connected with a separate path to the input capacitor ground. figure 20. component side. figure 19. application board layout. AN1088 application note 10/14
application ideas. the l6234 can be used in many different applications. typical examples are a half bridge driver using one channel and a full bridge driver using two channels. in addition, the bridges can be paralleled to re- duce the rdson and the device dissipation. the paralleled configuration can also be used to increase output current capability. channel 1 can be paralleled with channel 3 or channel 2 can be paralleled with channel 3. channel 1 should not be paral- leled with channel 2 because the sources of their low side dmoss are connected to the same sense1 pin . application ideas for the l6234 follow. figure 21. copper side. control logic l6506 +5v 100nf q r s q r s osc +5v rsense out3 l6234 en3 en1 en2 vs 100uf 1n4148 1n4148 in3 in2 in1 out2 out1 vboot vcp vs 10nf 220nf 100nf power so20 gnd vref sense2 1uf vsense constant frequency current control vcontrol +5v in1 in2 in3 reset en3 en1 en2 sense1 rx cx 1 fchop= __________ 0.69 rx cx for rx>10kohm figure 22. constant frequency current control AN1088 application note 11/14
low cost application with speed and torque control loops. a low cost solution to obtain a complete three phase brushless motor control application with speed and torque closed control loop is shown in fig. 23. this simple low cost solution is useful when high dynamic performances and accuracy of the speed loop are not required. the current regulation limit, which determines the torque , is given by vcontrol/rsense. the constant toff of the pwm is fixed by rx2 and cx2. the speed loop is realised using a hall effect signal, whose frequency is proportional to the motor speed. at each positive transition of the hall effect sensors the monostable maintains the pulse for a constant time , ton, with a fixed amplitude, v5. the average value of this signal is proportional to the fre- quency of the hall effect signal and the motor speed . an op-amp configured as an integrator , filters this signal and compares it with a reference voltage, vref, which sets the speed . the generated error signal is the control voltage, vcontrol, of the currrent loop. therefore the current loop modifies the pro- duced torque in order to regulate the speed at the desired value. the values of cf and r2 should be chosen to obtain a nearly ripple free op-amp output, even at low mo- tor speed. this constrain limits the system bandwidth and so limits the response time of the loop. the regulated speed, for a rotor with n pairs of permanent magnetic poles , is given by : w m = ? ? ? 1 + r1 r2 ? ? ? v5 ? ton ? n + 1 kg ? vref ? 60 [rpm] with kg = r4 r3 + r4 ? kt ? 1 rsense ? 1 b ? r2 r1 in which kt, expressed in [nm/a] , is the motor torque constant and b, expressed in [nms], is the total viscous friction. in most cases 1/kg can be neglected. hall effect sensors hall effect signals v s +5v 1/4 tsm221 q v5=+5v pwm out1 out2 out3 brushless motor speed loop l6234 power so20 control logic in1 in2 in3 en1 en2 en3 17 18 6 7 4 14 8 3 13 12 1q 13 1b hall effect signal 2 7 1 7 1 4 11 6 v sense 2 3 5 11 10 1,10,11,20 - + - + 16 2 19 5 15 gnd sense r sense 0.3 w c1 200nf r2 1m r1 100k ton 1/fe vm v5 r3 4k vcontrol 1/4 tsm221 r4 1k v5=+5v vref +5v rx2 cx2 912 6 16 3 15 1 14 8 +5v rx1 100k cx1 a (reference speed voltage) 1/2 m74hc123 monostable 1/2 m74hc123 monostable d01in1210 figure 23. complete three phase brushless motor application with speed and torque control. AN1088 application note 12/14
the ton values, given by kcx1rx1, must be less than the period of the hall effect electrical signal at the desired motor speed , so ton must meet the requirement of 1.1 : ( 1.1 ) ton < 60 n ? w m for the motor and the load used in this application, which have the following parameters : jt = 10 -4 [kg ? m 2 ] (motor plus load inertia moment); kt = 10 -2 [nm/a] ; b = 10 -5 [nms] n=4 ; r1=100k +/- 10% [k w ] ; r2=1m 1[kw] ; cf=220n [f] a regulated speed of 6000rpm can be obtained with an accuracy of around +/-3%, considering ton ac- curacy of +/-1% , the v5 and vref mismatch of +/-1% . if the speed is 6000rpm, there are 100 rotor revolution for second, with n=4, the hall effect frequency is 400hz. therefore ton has to be lower than 2.5ms (according to equation 1.1). the phase margin is about 45 and the response time of the speed loop for a speed step variation is around 200ms . 6x6 brushless application vcontrol constant toff pwm current control. two m74hc124 plus an lm339 thre e phase bru shle ss motor in1b in1a in2a en 2 en 1 out3 l6234 en3 en1 en 2 in3 in2 in1 out2 out1 vboot vcp vs vs 100uf 1n4148 1n4148 10nf 220nf 100nf gnd vref sen se1 1uf sense2 in3b in3a in2b en 3 out3 l6234 en3 en1 en 2 in3 in2 in1 out2 out1 vboot vcp vs vs 100uf 1n4148 1n4148 10nf 220nf 100nf gnd vref sen se1 1uf sense2 m74hc123 monostable +5v 100nf 23 16 4 15 14 8 1 +5v +5v 100nf lm339 470pf 1k 1 +5v 8 + - _ q a b 4 comparator & monostable comparator & monostable comparator & monostable control logic vsense1 vsense2 vsense3 pwm1 pwm2 pwm3 out1a out1b out2a out2b out3b out3a speed and position feedback figure 24. 6x6 three phase brushlees application circuit AN1088 application note 13/14
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com AN1088 application note 14/14

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